1. Field of the Invention
The present invention relates to a semiconductor device having a thin film transistor formed on a glass substrate, a method for manufacturing the same and a display device comprising the semiconductor device, and more particularly, to a semiconductor device whose impurity-doped region is activated by a laser annealing method, a method for manufacturing the same and a display device.
2. Description of the Related Art
A poly-silicon (hereinafter referred to as “p-Si” from time to time) thin film transistor (TFT), owing to its high driving capability in comparison to an amorphous-silicon (hereinafter referred to as “a-Si” from time to time) TFT, makes it possible to form a complex drive circuit which is difficult to form using an amorphous-silicon TFT. Further, as indicated by the recent announcement that a central processing unit was formed using a poly-silicon TFT, this is a technology that is attracting particular attention.
In general, poly-silicon TFTs are generally classified into high-temperature poly-silicon TFTs which are fabricated on quartz through a high-temperature step similar to a semiconductor wafer process and low-temperature poly-silicon TFTs the highest temperature for which during fabrication is suppressed down to about the heat resistance temperature of glass. Of these since the low-temperature poly-silicon TFT can be formed on a glass substrate, it is used as a display unit, such as a liquid crystal display device and an electro-luminescence display device, of electronic equipment such as a mobile telephone, a portable information terminal and a personal computer, and applications expected for a flat display device which is driven by an element which is formed on a glass substrate. (See Japanese Published Unexamined Patent Application No. 2001-177103 and Japanese Published Unexamined Patent Application No. 2001-217422, for example.)
Among the steps in manufacturing the low-temperature poly-silicon TFT, the step that requires the highest temperature for processing is the impurity-activating step. A thermal processing temperature at the impurity-activating step, although depending upon the impurity-doping condition, generally requires a temperature of approximately 500° C. While a batch-type furnace annealing is easy to adapt for the impurity activating step, in this case contraction of glass substrate occurs depending upon the type of substrate used and annealing temperature, because a glass substrate is heated at the same time together with a poly-silicon layer. Therefore, for impurity activation using an anneal furnace, it is necessary to use relatively expensive heat-resistant glass as the substrate or required the precompaction process.
Meanwhile, the excimer laser annealing (ELA) activation method has been proposed according to which excimer laser beam irradiated upon a surface of an impurity-doped region of a poly-silicon layer to heats up the poly-silicon layer and activates impurities. Although the ELA activation method realizes selective heating of only the poly-silicon layer without heating the glass substrate, if ELA activation is performed after a gate electrode is formed, because the gate electrode is exposed to laser irradiation, the heat of the laser could damage the gate electrode and the gate electrode could be deformed or quenched.
Noting this, conventionally, for ELA activation for a TFT, such a method has been proposed which permits heating only a selected area to be heated up to a high temperature without adversely influencing an area which should not be heated to a high temperature (See Japanese Patent No. 3211377 for instance.). According to the semiconductor device manufacturing method described in Japanese Patent No. 3211377, utilizing the phenomenon that the reflectance of light cyclically changes depending upon a thickness, a film whose thickness brings about a high reflectance is formed on an area which should avoid heating to a high temperature and a film whose thickness brings about a low reflectance is formed on an area which should be heated up to a high temperature. FIG. 1 is a cross sectional view showing a TFT structure in the semiconductor device described in Japanese Patent No. 3211377. As shown in FIG. 1, in the semiconductor device described in Japanese Patent No. 3211377, within an area partitioned by element isolation regions 102 in the surface of an Si substrate 101, there are a pair of highly-doped regions 111 that serve as a source or a drain and a pair of LDD (Lightly Doped Drain) regions 109, and on a channel region between the paired LDD regions 109, a gate electrode 107a is formed upon a gate insulation film 103. Further, there are sidewalls 110 at the both side surfaces of the gate electrode 107a, and a SiO2 layer 112 is formed covering these. In this semiconductor device, the SiO2 layer on the highly-doped regions 111 (the gate insulation film 103 and the SiO2 layer 112) is set to a thickness which minimizes the reflectance of laser beam, whereas the SiO2 layer on the gate electrode 107a (a SiO2 layer 108a and the SiO2 layer 112) is set to a thickness which maximizes the reflectance of the laser beam. Since this maximizes the reflectance of the laser beam on the gate electrode 107a but minimizes the laser beam in the impurity-doped region, it is possible to activate impurities while preventing deformation of the gate.
The semiconductor device described in Japanese Patent NO. 3211377 fabricated as the SiO2 layer 108a is formed on the gate electrode 107a in which a poly-crystalline silicon film 104a, a tungsten silicide film 105a and a poly-crystalline silicon film 106a are stacked in this order on top of each other, resist patterning is performed by photolithography, the SiO2 layer 108a, the poly-crystalline silicon film 104a, the tungsten silicide film 105a and the poly-crystalline silicon film 106a are dry-etched, thereby forming the gate electrode 107a, and the SiO2 layer 112 is then formed covering the entirety.
While the manufacturing method above described in Japanese Patent No. 3211377 is an invention on the assumption that a single-crystal silicon substrate is used, application of this method which requires forming the laser reflection film on the gate electrode to a TFT which is formed on a glass substrate has been studied (Japanese Published unexamined Patent Application No. 92836/1997 and Japanese Published Unexamined Patent Application No. 2000-138374, for example.). According to Japanese Published Unexamined Patent Application No. 92836/1997 and Japanese Published Unexamined Patent Application No. 2000-138374, an insulation film whose thickness corresponds to the wavelength of laser beam is formed on a TFT that comprises a gate electrode of a single-layer structure. To be more specific, in the poly-silicon thin film transistor described in Japanese Published Unexamined Patent Application No. 92836/1997, the thickness of an inter-layer insulation film on a gate electrode is set to such a range in which the transmittance of laser beam remains the lowest, thereby effectively reducing the energy of the laser beam which reaches the gate electrode and preventing the gate electrode from being peeled from gate inter-layer insulation film, and in a source region and a drain region, the total thickness of the gate electrode and the inter-layer insulation film is set to such a range in which the transmittance of the laser beam becomes the highest, thereby ensuring that the energy of the laser beam reaches the source region and the drain region and activation is taken palace efficiently. Meanwhile, the semiconductor device described in Japanese Published Unexamined Patent Application No. 2000-138374 is a semiconductor device in which a TFT is formed on a glass substrate, and the insulation film formed on an active region has a thickness which reduces the reflectance of the laser, whereas the insulation film formed on another area than the active region has a thickness which increases the reflectance of the laser beam.
However, the conventional techniques above have the following problems when applied to a large-area glass-substrate based fabrication process. That is, when a large-size glass substrate is used, the process becomes less uniform than where a silicon substrate is used, and therefore, it is difficult to form the gate electrodes of the TFTs and reflection films uniformly all over the substrate, which is a problem. Although TFTs with their gate structures consist of single-layer may have acceptable uniformity, in particular, as in the case of the TFTs described in Japanese Published unexamined Patent Application NO. H9-92836 and Japanese Published Unexamined Patent Application No. 2000-138374, TFTs those of having the gate structures consist of more than 2 layers in an attempt to control a threshold voltage and improve electric characteristics as in the case of the semiconductor device described in Japanese Patent No. 3211377, have inferior uniformity due to the process thus it is difficult to obtain similar shape all over the substrate.
A description will now be given on a problem which occurs when laser reflection films are disposed on gate electrodes while TFTs comprising gate electrodes of a multi-layer structure are formed on a large-size glass substrate, with reference to an example of TFTs comprising gate electrodes having a double-layer structure in which a Cr layer and a micro-crystalline silicon (hereinafter referred to as “μc-Si” from time to time) are stacked up. FIG. 2 through FIG. 4 are cross sectional views showing a problem which occurs when a laser reflection film is formed on a gate electrode having a double-layer structure, and in each drawing, A shows a center of a substrate, whereas B shows a periphery of the substrate. In cases where a SiO2 layer 128 which is a laser reflection film is formed on a gate electrode having a double-layer lamination structure in which a Cr layer 127 and a μc-Si layer 126 are stacked up, first, an underlying insulation layer 122 is formed on the entire surface of a glass substrate 121, and after a poly-silicon layer 124 which forms an impurity-doped region 123 is formed on the underlying insulation layer 122, a gate insulation layer 125 is formed so as to cover the poly-silicon layer 124. After the μc-Si layer, the Cr layer and the SiO2 layer are formed in this order on the gate insulation layer 125, a resist pattern for the gate electrode is formed by photolithography, thereby forming a TFT in which the SiO2 layer 128 is formed by dry etching on the gate electrode in which the Cr layer 127 and the μc-Si layer stacked up.
However, in the TFT having this structure, under a condition which results a desired shape as designed in the center of the substrate as shown in FIG. 2A, a side-etched portion 129 occurs in the μc-Si layer 126 within the periphery of the substrate, and further, an over-etched portion 130 occurs in the gate insulation layer 125 as shown in FIG. 2B. Meanwhile, under a condition which results a desired it possible to obtain a shape as designed in the periphery of the substrate, as shown in FIG. 3B, etching of the μc-Si layer 126 is insufficient within the center of the substrate, and a film remaining portion 131 is formed as shown in FIG. 3A. Although the center of the substrate becomes as designed as shown in FIG. 4A as a result of etching which is executed under such a condition that will not create the side-etched portion 129 and the over-etched portion 130 as those shown in FIG. 2B, and the film remaining portion 131 as that shown in FIG. 3A, the SiO2 layer 128 which is a laser reflection film overhangs within the periphery of the substrate as shown in FIG. 4B. When the SiO2 layer 128 overhangs, the coverage of the overlying inter-layer film becomes insufficient and therefore disconnections, short circuits and the like are generated. These problems are attributable to the inferior uniformity of the process unique to the large-size glass substrate and to different etching rate characteristics between Cr and μc-Si.
Note that in the actual fabrication process of low-temperature poly silicon TFT applications, the problems shown in FIG. 2B, FIG. 3A and FIG. 4B can occur simultaneously in any combination with each other in case the gate structure of choice for the TFT is consist of more than 2 layers of different materials that have different etching speed.